Do I Need to Compile Again After Scan Insertion

By Namrata Makwana (eInfochips, an Pointer company)

Abstract

Design For Testability(DFT) adds an extra Hardware/Structure in the existing functional design too chosen MBIST/Scan insertion to become controllability and observability of the blueprint to make information technology easily testable after manufacturing i.e., postal service-silicon SOC testing.

Simulation'southward pivotal role is to check if the binary response applied equally an input that matches the values at the output response of the chip. Based on the matching responses of the circuit, goodness of fleck will be defined, which in the end concludes the quality of the chip.

In this article, we are going to understand how nosotros can solve the gross simulation failure by understanding and editing the SPF skeleton at ATPG stage.

Keywords: DFT (Design for testability), ATPG (Automatic test pattern generation), Simulation/Pattern validation, SPF (STIL protocol file).

Introduction

ATPG (Automated test design generation) is the process of generating the test vectors for the particular test manner to bank check the manufacturing defects, which is farther used by simulation tools for validation. ATPG is performed on scan inserted blueprint and the SPF generated through browse insertion. Simulation is the afterward stage subsequently ATPG, for the validation of the patterns generated in different formats.

All the stages are interdependent on each other.
Refer below figure to bank check the interdependency of all the stages.

Fig.one.1 – DFT Stages

• Simulation/Pattern validation plays a vital office in DFT, in order to examine the vectors generated by the ATPG tool.
• Once the blueprint is prepare with scan inserted netlist, exam vectors will be generated and the same vectors will be used for simulation.
• If any Fault or severe warnings occurs at ATPG/vector generation phase, it can either be solved at the same stage, else nosotros demand to jump to Scan phase for the required changes which helps to clean ATPG issues.
• If the blueprint simulation failure occurs, we need to analyze the failure and need to do necessary changes in ATPG stage similar spf modification to clean up the simulation failures.

What is SPF?

SPF stands for STIL(Standard test interface linguistic communication) protocol file generated after the scan insertion phase, which consists of all the necessary and basic browse data.

In general words, SPF portrays the information of scan structure, scan chain, initial state value for all the signals for particular test mode and furthermore.

All the to a higher place-defined information in SPF is needed to guide the ATPG tool for DRC checks and blueprint formatting.

SPF is assigned at the run_drc stage to verify the compatibility of scan inserted netlist with the SPF, it farther determines how the scan structure tin be used to generate patterns and fault simulations.

Delight cheque below SPF infrastructure segment for a more than detailed structure of SPF.

Synopsis Tetramax ATPG catamenia till DRC

Fig.ane.2 – ATPG catamenia till DRC

Basic ATPG menstruum

• Read scan inserted netlist
  • Scan outputs are carried forrad equally ATPG inputs.
• Read libraries
  • Read standard jail cell libraries, target libraries, link libraries and other necessary libraries in Verilog format
• Build model
  • Build the model based on the last unreferenced module read by the read_netlist command, it also flattens the design for further need.
• Ready fault model
  • Ready the fault model transition or stuck based on your requirement
• Run drc
  • Checks the compatibility of scan inserted netlist with SPF for pattern generation.
  • If Error observed, analyze the error and make changes in SPF or netlist accordingly

SPF Skeleton

Allow'due south brainstorm with the dissimilar segments categorized in SPF, described below:

1. Signals
2. Signal groups
3. Browse structure
4. Timing
5. Procedures
6. MacroDefs

The SPF which is described in this article is based on stuck-at faults without compression.

one.Signals

It is the beginning section of SPF containing definition of all the signals with their type(In, Out, InOut etc)

two.Signal Grouping

In this section, the signals which were divers in the outset office is classified based in dissimilar group based on its type.

The group signals further used to provide constraint value at different procedures.

• Below shown are some bespeak groupings:

"all_in" "all_out", "all_ports", "all_bidi", "_pi", "_po", "_si", "_so"

3.Browse Construction

This section includes the scan concatenation data like scan chain name, Scan_in, scan_out and scan_enable pin and likewise the clock used past that particular chain.

four.Timing

Waveform table is defined in this department which includes the description of the different values provided to different signals like clock period definition, reset value, test mode value etc.

Waveform table is defined for all the different procedures which are required for dissimilar apply :

• Default_WFT
• Multiclock_capture_WFT
• Allclock_capture_WFT
• Allclock_launch_WFT
• Allclock_launch_capture_WFT

Note:

• "Default_WFT" is used for loading and unloading of the vectors, or nosotros can say for shifting purpose.
• Among all the in a higher place-divers WFT, multiclock_capture is the default capture process for all the fault models, always used by the Stuck-at fault model.
• "allclock_*_WFT" is used for at-speed testing, you tin can the clock frequency based on the requirement for the capture procedure.

5.Procedure

Procedures are defined for the capture bicycle of stuck-at and at-speed faults like Multiclock_capture, allclock_capture, allclock_launch, allclock_launch_capture procedures.

Based on which fault model y'all are using, the capture procedure will be automatically selected.

Example of ane capture procedure, and how its structure looks similar:

//Default capture process in All SPF – multiclock_capture
"multiclock_capture" {

a. W "Multiclock_capture_WFT_";
// Waveform tabular array for multiclock_capture will be used hither

b. C {

i. "all_in" = 00 \r4 North 1011;

//values divers for indicate group "all_in".
//We just demand to map the value defined in C argument with the signals mentioned in the "all_in" signalgrouping.
//clk_1 = 0; clk_2 = 0; ScanIn_1 = N; ScanIn_2 = Northward; Input_1 = N; Input_2 = N;
rstn_L = 1;(Active low reset so it should be one to conciliate in capture), scan_enable = 0; (Scan enable should be 0 for capture), scan_mode = 1; test_mode = 1

ii. "all_out" = \r4 X;
//All_output are Ten, as we does non know information technology'due south initial value, information technology will exist capture later and automatically observed.

iii. "All_bidi" = \r1 Z;

}

iv. F {
"Scan_enable" = 0;
"Scan_mode" = 1;
"clk_1" = P;
"clk_2" = P;
"rstn_L" = i;
}

//F section contains the signals which needs to exist inverse after its initial state value or abiding value.
//clock divers every bit 0 in "C section" of procedure to provide it initial value, we demand it to be pulsed.

c. V {
i. "PI" = \eleven #;
two. "PO" = \v #;
}
}

// Total PI and PO numbers with # is the placeholder for the values which is going to be generated for all the signals.

vi.MacroDefs

This partition includes the examination setup part through which we can initialize the instruction and data bit registers at the TAP/top level.

Also, the exam setup is required to provide the values to the signals before the design generation starts for the scan mode to bring chip in its known land like functional mode, test way, MBIST mode, etc.

What is Simulation failure?

Vectors generated by ATPG applied to the simulation stage to check the validity of the signals and nets for a sanity check of the browse inserted netlist.

If the input vectors provided for simulation don't match with expected or gold output leads to simulation failure.

It is always necessary to clean the simulation without whatever mismatch to make certain the perfection of browse insertion.

Simulation Failure debug and its solution:

To debug the mismatches that occurred during the design validation, we need a specific tool to check the waveform signals value like ncsim, Verdi, etc.

To debug, kickoff of all, accept the absolute path of the failing register and analyze the value of the mandatory signals like clock, reset, D, SI, SO, Q, etc.

If any X value observed in the signal, then back-trace the particular signal and practice this until the source for X generation is observed.

1. Clock value X
2. Reset value 10
3. Clock Frequency non right

Clock value Ten

• In the beneath-shown waveform, scan_clk, CLK, Scan_en, reset, test_mode and scan_mode is getting X value after some amount of time extent.
• Initialization value seems to be 0 or 1, and after that, it'southward getting X throughout for few signals and some it is having similar beliefs for the whole point.
• Get-go of all, for debugging any simulation mismatches, check all the point value for mandatory signals which illustrate the browse signals like scan clock, scan enable, scan fashion, scan reset, etc.

On further dorsum tracing the scan_clk and RESET_L signals, below source test_mode – Ten and scan_clk – ane is observed.

Information technology is observed that the value of the clock is ceaselessly 1 and test_mode is 10.
Now the question arises in mind that How to resolve? Where to fix? How to fix?
So, here are the reply explained below for the above question.
We tin force value while performing simulation to temporarily clean it.
Too, to fix the issue without any force given at the simulation stage, we tin check the values of the particular signals in SPF used at the ATPG stage.

Here comes the SPF editing role to define the scan_clk and test_mode values.
Before the values for scan_clk and test_mode is inaccurately divers in the SPF equally shown below:

In this, "All_in" values are defined based on the signals and its position.

As described in the SPF infrastructure section, the values of required scan signals should be ready properly in the procedures portion.

Round mark are drawn on the outcome part, and below is the description of that.

Scenario 1:

In "multiclock_capture" procedure, "All_in" values are not correct as shown below:

"All_in" = xi \r8 N;
//
C {
"All_in" = '"scan_clk = i" + "clk =1" + "ScanIn_1 = N" + "ScanIn_2 = N" + "Input_1 = Northward" + "Input_2 = Due north" + "rstn_L = Due north" + "scan_enable = Due north" + "scan_mode = N" + "test_mode = Due north"';
}

F {
"scan_clk" = P; //scan clock is pulsing, it will override the value in C section, so clock will pulse in capture cycle.
}

Solution ane:

C {
"All_in" = 00 \r4 N 1011;
}

F {
"scan_clk" = P;
"test_mode" = 1 //It should be throughout 1 for all the process.
}

Scenario 2:

In "load_unload" procedure – Clock should be pulsing for shift procedures.

In beneath scenario clock is defined constant ane.

C {
"All_in" = 11 \r8 N;
}

Shift {
V {
"Clock" = 11;
} }

Solution 2:

C {
"All_in" = 00 \r4 Due north 1011;
}

Shift {
V {
"Clock" = PP; // clock should be pulsing while shifting
} }

Scenario iii:

If the scan clock frequency is different than the required frequency, and so change the clock period in _WFT table, as shown beneath:

"scan_clk" { P { '0ns' D; '35ns' U; '65ns' D; } }
"clk" { P { '0ns' D; '25ns' U; '75ns' D; } }

Change the period in ns for the up and down department of the respected scan clock according to the required frequency.

SPF is also used to feed instructions and data bits to the UTDR (user defined test information register bits) and for initialization/test setup purpose as well.

Decision

With the increment in applied science node, Silicon industry testing has go challenging.

To bargain with the failures in SoC we need to invest significant amount of time and effort.

In a higher place commodity presents different methods to solve the SoC failures efficiently past performing the modifications in the SPF file.

Writer

Namrata Makwana

Namrata makwana works as an ASIC DFT Engineer at eInfochips, an Arrow company. She has 3 years of experience in ASIC DFT, which includes working on various engineering nodes, from 28nm to 7nm, handling a verities of DFT tasks on block level and top level.

References

1. TestMAX™ ATPGandTestMAXDiagnosisUserGuide, VersionQ-2019.12,December2019
2. P1450.1 IEEE Standard Exam Interface Linguistic communication (STIL) for Digital Examination Vector Information Design Extension P1450.1 Working-Draft 14, Aug 1, 2002
3. Rahul Malhotra ∗ , Sujay Deb†, Fabio Carlucci‡, "A novel arroyo to Reusable Time-economized STIL based blueprint development" 2022 IEEE
4. Micross component "STIL Language Test Vector Format (Simplified)"
5. STIL-based Semiconductor Test Activity Group (SSTAG), IEEE Std 1450.0-1999, Revision 6.twenty Oct. 17, 2011

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Source: https://www.design-reuse.com/articles/47949/reduce-atpg-simulation-failure-debug-time-by-understanding-and-editing-spf.html